The potential for electrostatic discharge to cause damage to integrated circuits is well known. Electrostatic discharge may occur at various stages in the assembly and testing of a chip package, and may be generated by a variety of sources. To prevent damage to the chip, electrostatic discharge (ESD) protection devices must be built into the chip to dissipate ESD voltage/current spikes.
Existing ESD protection devices typically comprise a shunt connected between each input/output (I/O) line and ground and/or a power supply. These devices frequently contribute an undesirable level of parasitic capacitance to the I/O lines. This capacitance can adversely affect circuit performance, particularly in the field of radio frequency (RF) circuits.